1. Field of the Invention
This invention relates to the field of computer systems, and in particular to processor instruction sets.
2. Description of Related Art
Computer systems utilize xe2x80x9cbranchxe2x80x9d instructions to control program flow. In a conventional computer system comprising a processor and a memory that contains program instructions, the processor executes each program instruction in the memory in sequential order, one instruction at a time. A branch instruction is used to execute program instructions that are located at a specified location in memory, thereby altering the default execution of instructions at sequential memory locations. A conditional branch is used to either continue to process the instructions in sequential order, or to branch to a specified location in memory, depending upon a given condition. The condition is tested, and if the condition is true, the computer processor continues execution at a specified address, otherwise, the processor continues execution at the next sequential location.
Other flow-of-control instructions are also available in most computer systems, such as a subroutine or function xe2x80x9ccallxe2x80x9d and a corresponding xe2x80x9creturnxe2x80x9d. (For ease of reference, a function is considered hereinafter as a subset of a subroutine). As in a branch instruction, a subroutine xe2x80x9ccallxe2x80x9d is used to execute program instructions that are located at a specified location. In contrast to the branch instruction, a call instruction also causes the processor to store the address of the next sequential instruction after the location of the call instruction (the xe2x80x9creturn addressxe2x80x9d). In this manner, a corresponding subroutine xe2x80x9creturnxe2x80x9d instruction will cause the processor to continue execution at the stored return address. Conditional call and return instructions operate similar to the above referenced conditional branch instruction.
The conventional branch and call instructions include two items: an operation-code (op-code) that identifies the instruction as a branch or call instruction, and the address at which the next instruction is located. A conventional return instruction, on the other hand, only includes the operation code. The conventional conditional branch, call, and return instructions are similar to the unconditional branch, call, and return instructions, except that alternative op-codes are used to identify the alternative condition(s) that are used to determine whether to branch to a destination-address or to continue with the next sequential instruction after the conditional instruction.
Typically, an application program contains many branches and subroutine calls, and often branches and subroutine calls to the same destination address are used repeatedly. For example, a xe2x80x9cselect-casexe2x80x9d programming construct allows different segments of program instructions to be executed, depending upon a value of a given parameter, such as a xe2x80x9cfiling-statusxe2x80x9d parameter (single, married filing jointly, married filing individually, etc.) in an income tax preparation application program. Within each different segment of the program corresponding to the value of the given parameter, the same subroutines may be called, albeit with different determined arguments, or with a different combination or order of subroutines, or with a different set of conditions, and so on. Because each conventional branch or call command requires the inclusion of the destination-address, a significant amount of address redundancy exists in a typical program. Subroutine return instructions do not incur this address redundancy penalty, but are limited in use to causing a return from a subroutine call.
The evaluation of conditional instructions in a-typical program application can also be problematic. A typical processor includes a set of xe2x80x9cflagsxe2x80x9d, and a conditional instruction effects an operation, such as a branch, return, or call, in dependence upon the state of one or more of these flags. Different instructions affect the state of different flags. For example, some instructions affect all flags, some instructions affect no flags, other instructions affect select flags, and so on. A common programming xe2x80x9cbugxe2x80x9d occurs when a change is made to a program that uses an instruction that affects flags, without an exhaustive assessment of the effects that a potential change in the state of each flag will cause. Because the added instruction may result in the same flag state as the intended flag-setting instruction, this error may not be immediately detected, and the effects of the error may not be associated with this change.
In a typical high-performance computer system, instructions are pre-fetched from memory so that they are available to the processor for execution as soon as the processor is ready to execute the next instruction. In a typical pre-fetch operation, the system pre-fetches a block of sequential instructions from the system memory into a block of memory that is local to the processor, and therefore immediately available to the processor. When a branch occurs, the previously pre-fetched instructions that sequentially follow the branch instruction in memory are replaced by the instructions from the memory at the specified destination address. This replacement incurs a performance cost while the processor waits for the next instruction from the system memory. Most systems include a xe2x80x9clook aheadxe2x80x9d capability, wherein the pre-fetch operator looks ahead in the program code being executed to identify the next branch of control. When an unconditional branch is detected, the pre-fetch operator pre-fetches the information from the specified destination-address so that it can provide it to the processor immediately after the branch command is processed. The use of pre-fetching for conditional branch instructions is substantially more complex, because it is unknown whether the next instruction executed after the branch instruction will be the instruction at the destination address or the instruction immediately following the branch instruction. If sufficient local memory is available, segments of instructions from both areas of the system memory are pre-fetched. Alternatively, or in addition to this multiple pre-fetch technique, predictive techniques are often used to pre-fetch the instructions that are likely to be executed. Such predictive techniques are subject to a high degree of variability because in most cases, the state of the condition is virtually unpredictable.
It is an object of this invention to enhance the efficiency of a computer system. It is a further object of this invention to enhance the reliability and maintainability of a program operated on a computer system. It is a further object of this invention to improve the predictive aspects of a pre-fetch system. It is a further object of this invention to ease the task of program development.
These objects, and others, are achieved by providing an architecture that supports the decoupling of parameters typically associated with branch instructions. Branch and call instructions are provided that do not contain an explicit destination address; and, branch, call, and return instructions are provided that do not contain an explicit test condition. In accordance with this invention, the processing system provides a xe2x80x9cdefaultxe2x80x9d value to any control element in the processor that is not expressly controlled by a particular instruction. In the case of a branch or call instruction, the default destination-address provided to effect the branch or call is the destination-address provided by a prior instruction. Subsequent or alternative branch or call instructions branch to this same address until the default address is set to a different address. In like manner, in most cases, the default condition that is used to determine the result of a conditional test, such as a conditional branch, call, or return instruction, is the last condition specified in a prior instruction. To further support the above objects of this invention, and others, condition-testing can also be effected prior to the execution of conditional instructions. By decoupling the specification of the condition and/or the destination address from the instructions that cause a branch, call, or return, these instructions can be configured to effect other operations, such as modifying registers or memory elements in preparation for processing by the routine to which the program branches or returns. Also, by providing an explicit means for setting a subsequent default destination address and by providing an explicit means for preevaluating a condition flag, program development and maintenance costs can be expected to decrease, and the variability associated with predicting the outcome and destination-address of conditional branches can also be expected to decrease.